The present invention relates to a semiconductor device for use in evaluating an integrated circuit device. More particularly, this invention relates to an evaluation tool for evaluating initial characteristics and reliability of an LSI (Large Scale Integrated Circuit).
Recently, the integration density of LSIs has been increased more and more. On the other hand, the possibility of occurrence of a passivation crack or Al slide in the LSI has become higher. It is known that such drawbacks occur due to a thermal stress (shearing stress) resulting from a temperature variations in a resin-sealed package. In general, the thermal stress applied to the resin-sealed package increases as the wiring becomes finer or the chip becomes larger in size.
The passivation crack is a factor of deterioration in the humidity resistance of the resin-sealed package. In particular, in the case of a product with double-layer AL wiring, a crack occurring in an interlayer insulation film deteriorates insulation between wiring layers. Depending on a pattern design (layout), an Al slide may cause inter-wire short or break of wire.
A method using TEG (TEST Element Group) is known as a prior-art method for diagnosing occurrence of defects such as passivation cracks or Al slide. This method was made public in the xe2x80x9c19th Symposium of Reliability and Maintenancexe2x80x9d of the Science and Technology Association (June 1989). According to this method, a TEG, in which a plurality of Al wire elements having varying widths in a range of 1 xcexcm to 90 xcexcm are two-dimensionally arranged, is assembled on a resin-sealed package. With this structure, the surface of a chip is observed before and after a thermal stress is applied to the chip in a thermal shock test, etc. Thereby, a region on the chip, where a passivation crack or Al slide has occurred, is quantatively evaluated.
There is known another method wherein a stress within a package is measured using a stress measuring element in which diffused resistance layer patterns (unit cells) with different piezoresistance coefficients are two-differentially arranged.
In the TEG or the stress measuring element, however, the Al wire elements are resistance layer patterns are arranged only two-dimensionally. Thus, their structures are greatly different from the structure of products with double-layer Al wiring. Therefore, neither of the above-described prior-art methods is suitable for finally evaluating products. In the prior art, for this reason, it is imperative to evaluate actual products one by one.
The object of the present invention is to provide an evaluation tool (a semiconductor device for use in evaluating integrated circuit devices) capable of quantatively and precisely evaluating the initial characteristics and reliability of LSIs, and dispensing with evaluation using actual products.
In order to achieve this object, there is provided an evaluation tool comprising: a stress sensor, a temperature sensor and a resistor group which are all disposed on a semiconductor substrate; and a wiring layer provided on the stress sensor, the temperature sensor and the resistor group, with an insulation film interposed.
According to this invention, there is also provided an evaluation tool comprising: a semiconductor substrate; a stress sensor disposed at each of at least two locations including a central area and a corner area of the semiconductor substrate; a temperature sensor disposed close to the stress sensor at each of at least two locations including the central area and the corner area of the semiconductor substrate; a resistor group disposed in an array fashion on the semiconductor substrate excluding the locations where the stress sensor and the temperature sensor are provided; and a wiring layer provided on the stress sensor, the temperature sensor and the resistor group, with an insulation film interposed, the wiring layer being divided into a plurality of areas with different line widths ranging from several xcexcm to several-hundred xcexcm.
According to the evaluation tool of the present invention, defects which may actually occur in LSIs can be reproduced with higher fidelity. Thus, evaluation with a structure substantially equal to the structure of an actual product can be made.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.